This invention relates to a semiconductor device with a gate electrode formed of a conductive layer which consists of a polysilicon layer and a metal-silicide layer, and a method for manufacturing the semiconductor device.
To reduce the resistance of a polysilicon gate electrode or a polysilicon wiring layer, metal-silicide such as TiSix is provided on polysilicon in MOS semiconductor devices. This structure is obtained by sequentially depositing polysilicon and TiSix on a gate oxide film.
It is generally known that a laminated structure of TiSix and polysilicon is not stable at a high temperature, since TiSix grains enter polysilicon and the resultant TiSix layer is divided into portions when they grow. This phenomenon is generally called as an "inversion or agglomeration phenomenon". If such a phenomenon occurs at a gate electrode, the sheet resistance of the gate electrode becomes extremely high, and the quality of the gate oxide film is degraded.
Referring to FIGS. 1A and 1B, the inversion phenomenon will be described. As is shown in FIG. 1A, a TiSix layer 32 is formed on a polysilicon layer 31 by DC sputtering at a temperature of, for example, 300.degree. C. or less. At this time, the TiSix layer 32 is in an amorphous state. Subsequently, the TiSix layer 32 is crystallized in a process in which an SiN layer (not shown) is deposited using the LP-CVD, or in a process in which a side-wall of a gate electrode is oxidized at high temperature. During the crystallization and the grain growth, the grains of the TiSix layer 32 enter the polysilicon layer 31 and also the layer 32 is divided into potions, as is shown in FIG. 1B. Experiments show significant variations in the sheet resistance of the TiSix layer, which resulted from the inversion or agglomeration phenomenon caused by the high temperature process.
FIG. 2 is a perspective view, showing a state seen while a gate electrode consisting of polysilicon and TiSix is formed on a gate oxide film by the conventional method. As is shown in FIG. 2, a polysilicon layer 42, a TiSix layer 43 and an LP-CVD SiN layer 44 are formed in this order on a gate oxide film 41. The gate oxide-film 41 is formed on a Si substrate 40.
As aforementioned, the TiSix layer 43 is crystallized in the high temperature process for forming the SiN layer 44. The state resulting from the inversion phenomenon due to the high temperature process is shown in FIG. 2.
The SiN layer 44 in FIG. 2 is thereafter patterned and used as an anti-etching mask to selectively etch the TiSix layer 43 and the polysilicon layer 42 in order to form a gate electrode. The inversion phenomenon having occurred during the formation of the SiN layer 44 will cause a disadvantage as below. Reference numeral 45 in FIG. 2 denotes that portion of the gate oxide film 41 which reacted with TiSix.
FIG. 3 is a perspective view partially in section, showing a state obtained after the gate electrode is patterned by RIE. As is evident from FIG. 3, etching pits 46 which degrade the quality (e.g. the breakdown voltage characteristic) of the gate oxide film 41 are formed in the gate oxide film 41 after the RIE process, because of reaction between the TiSix layer 43 and the gate oxide film 41 due to the inversion.
As described above, in the conventional case, the inversion phenomenon occurs due to the high temperature process during the formation of a laminated structure of TiSix and polysilicon, which makes it difficult to manufacture a semiconductor device with excellent electrical characteristics.